Synchronous communication is currently applied to realize a high data transmission rate of a dynamic random access memory (DRAM); however, when the DRAM develops more advanced and higher-speed, e.g., a double data rate three synchronous dynamic random access memory (DDR3 SDRAM), a circuit implementing a phase locked loop (PLL) and an analog delay signal line to realize synchronous communication cannot meet requirements of a high data transmission rate DRAM due to fabrication limitations. In addition, a signal is transmitted between the PLL and the analog delay signal line via an analog signal form; however, since a voltage of an analog signal is easily affected by noises, errors of data access time points or signal levels of the DRAM occur—such a problem is especially serious for the high data transmission rate DRAM.